In recent years, with the increase of network traffic, special processors called network processor dedicated to high-speed packet processing have been greatly developed. Network processors are processors specialized for processing network traffic. A network processor functions as a network interface in an information processing device, and performs packet processing and the like.
Network processors are programmable processors, and can change configurations of codes and queues of a pipeline, and peripheral resources including a memory and a table. An information processing device generally includes, in addition to the network processor, peripheral hardware such as a central processing unit (CPU) and a field programmable gate array (FPGA), a table, and the like. By downloading setting data, such as pipeline codes and register setting, written in a flash memory or the like to the network processor via the CPU, configuration is performed. Moreover, there is a case that configuration of the network processor is performed on command basis from the CPU through an application programming interface (API).
Network processors have an architecture separated into a control plane that performs a route control and the like and a data plane that performs packet transfer processing. The data plane has a pipeline structure, and performs packet processing of transfer destination determination and the like at high speed, referring to information in a table. The control plane controls operation and configuration of the data plane, through the API. The processing performed by the control plane includes table update processing.
As for pipeline processing performed in the data plane, processing to be performed is fixed in each phase, and a table to be accessed is also fixed in each phase. The network processor has a packet memory, and a packet of a subject of processing is shifted in the packet memory with transition of phase in the pipeline processing.
Furthermore, the table used in the pipeline processing is stored in a ternary content addressable memory (TCAM) or a random access memory (RAM). The network processor reads information in the table by using a search key or an address. The search key and the addresses are determined based on an input port number, information included in an input packet, a table read result in a previous stage, and the like.
A network administrator updates various kinds of tables when the network configuration is to be changed. In some cases, the network administrator updates more than one table.
As a conventional technique relating to network processors, there has been a technique in which a header including a search key is allocated to a received packet, and processing is performed in stages while repeating communication transmission and reception of the packet between a packet processing unit and a search engine (Japanese Patent Laid-open Publication No. 2007-208963).
However, when multiple tables are to be changed, there is a possibility of occurrence of a state in which consistency is lost between information in a table that has already been updated and information in a table that has not been updated. In that case, if the pipeline processing is performed using those tables under the condition that a table that has been updated and a table that has not been updated are not consistent, an improper processing result can be obtained.
Accordingly, to prevent the inconsistency occurring at the time of changing multiple tables, the following method has conventionally been applied to processing. The method is to suspend all processing temporarily in a network processor until update of all tables is completed, to disable dequeue and accumulate in an input queue, and then to enable dequeue to resume the pipeline processing after the update of all tables is completed. By processing by such a procedure, packet processing is performed in a state in which all tables are updated without inconsistency.
However, when the number of accumulated queues reaches an upper limit of the queue memory, packets overflowing therefrom are discarded. The discarded packets are to be retransmitted, to cause increase of traffic or transmission delay of packets, resulting in throughput degradation of the information processing device. In the method of suspending all processing and accumulating all input packets in queues, many packets can be discarded to degrade the throughput of the information processing device.